Showcase Design : 2D-DCT/IDCT

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Feature List
  • Low Power - an estimated 1/3 power consumption of other offerings seen on the market;
  • High Throughput - architecture achieves 0.25 clks/symbol, compared to a typical 1clk/symbol from other offerings on the market. Xilinx XC2V1000 implementation achieves 70MHz operation. This particular implementation therefore is capable of SXGA (1280x1024) at 100Hz with 4:2:2 component video. This high performance enables VGA (640x480) operation at just 3M84Hz for 25Hz 4:2:2 component video. This very low clock frequency (as well as low power detailed design) leads to the very low power consumption.
  • The IDCT function is IEEE1180-1990 compliant;
  • Small area - comparable with other offerings on the market;
  • Available with optimisations for ASIC or FPGA implementation;
  • 2's complement 9bit pixel data, 12bit DCT coefficient (8bit pixel, 11bit DCT supported);
  • Output saturation logic included;
  • Flow control signals on input and output interfaces;
  • Pipelined design;
  • Latency of 19 clock cycles;
  • DCT only and IDCT only variants can be made available for even smaller area and power consumption.

Available now for purchase. Why not replace your existing DCT IP, whether bought-in or in-house, whether stand-alone or part of a JPEG/MPEG function, with one that consumes perhaps only 1/3 of the power?

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