IC Development Services


Tools
The tools identified in the table below have been chosen due to their capabilities and also due to the current skill set within Jaskay Technology. Other tools will be considered if they are part of your preferred flow. We will arrange appropriate training for the engineers involved where necessary.

We are able to offer services in much of the typical IC development flow and will proactively work with a customer when minor gaps in tool knowledge exist. We can offer services in IP design, verification and code coverage, integration, synthesis, test insertion, STA, ATPG vector generation, formal verification and FPGA prototyping:-

Service Offered	Tasks Involved	Tools Required	Inputs from Customer	Deliverables to Customer
Formal Verification Phase 1 and 2 - Click here to see flow	RTL Technology Library and netlist Compilation. Name Matching and constraint setting. Equivalence Checking	Mentor Graphics FormalPro	RTL (if required) Various netlists (see FV flow) Technology Library	Compliance Report Documentation
ATPG - Test Assessment and Test Vector Generation Phase 1,2,3 and 4 - Click here to see flow	Testability Review Test Vector Creation Test Vector Simulation	Mentor Graphics Fastscan, Flextest, DFT Advisor. Mentor Graphics Modelsim Synopsys Tetramax	Scan Inserted netlist & SDF Optional Access to RTL and Synthesis scripts Fastscan compiled Technology Library	Suggested RTL changes Suggested Syntheses script changes Tester Vector Sets Test Coverage report Documentation
Code Coverage Phase 1,2 and 3 - Click here to see flow	RTL simulation, generation of coverage figures. Test-bench coverage review	Transeda VN-Cover Mentor Graphics Modelsim	RTL & Test-benches Coverage Requirements	HTML Code Coverage Reports Documentation
IP Development (Module or sub-block) or modifications to existing customer IP Existing or new IP integration FPGA Prototyping Synthesis, Test Insertion & STA Phase 1,2,3 and 4 - Click here to see flow	RTL Coding Test-bench authoring and IP verification Porting existing test-benches to top level of integration. IP Synthesis and Test Insertion. STA and timing closure for chip FPGA Place and Route Hardware	Mentor Graphics HDL Designer (optionally) Mentor Graphics ModelSim Synopsys DC and PT for ASIC or Leonardo Spectrum/Precision for FPGA. Xilinx ISE foundation & Chipscope Pro. Nallatech DIME development boards or other	Specification Re-used RTL code Re-used test-benches Re-used Synthesis and STA scripts Re-used constraint files	RTL code & test-benches designed to specification Verified RTL code Synthesis script Documentation netlist PAR script for FPGA Documentation. PAR nettlist. Compliance Matrix Documentation

We look to build a long term relationship with customers where we come to understand their development flow to the point where we can add value by providing advice on new tool capabilities and flow improvements.

Our Windows XP VPN and site-to-site secure VPN capabilities enable us to provide flexible and cost effective IC development services. Our service flows are divided into phases where some phases will require intense activity while others are a monitoring activity. The customer is invoiced according to the time required for the activity, which means that you pay less during the monitoring phases. The Windows XP VPN and site-to-site VPN means that we are also able to offer post-development service support very effectively.



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