IP Development Service


IP Creation, Modification, Integration, Verification, Synthesis, Test Insertion & STA. This process is illustrated below:






Phase 1 - Assessment of IP
The majority of design work today is the modification of existing modules or sub-blocks of chips already in production. These often do not exist as release-state IP with complete design documentation, testbenches, synthesis scripts, etc.

It is important as a first step to assess the design data, to determine what deliverables are required and what exists already in partial or complete form (testbenches, scripts, documentation).




Phase 2 - System Level Analysis and Development
Through discussions with your team the split of responsibilities for the system level development must be determined.

For example, in the case of the creation of a new IP, the functional specification may already be written (or at least known by) your systems team. Effort may be required in the creation of the various strategies for the design (clocking, reset, power, area, verification, prototyping and production test) for a particular target and possibly prototyping technology.

In the case of module re-use, the target technology may have changed, and so may have some of the system level strategies for the new chip. The implications of these changes need to be worked out and issues resolved.




Phase 3 - RTL Development
Once the specification is known the RTL and testbench code may be written. The coding standards and verification strategy must be followed. Code coverage is recommended.

Any testbenches written or used may be ported to integration testing of the module with other modules in the system, in order to further verify the module interfaces.




Phase 4 - Synthesis and Netlist Verification
Whether prototyping on FPGAs or creating a netlist for an ASIC technology, a broadly similar flow applies. Based on the target technology, constraints need to be set for synthesis and STA along with Formal Verification (where possible) performed in order to verify that those constraints were successful in producing the required design at gate level.

For both ASICs and FPGAs, simulation of the netlist using the appropriate testbench is required, and for FPGAs, development board prototyping may then take place. The target technology must be carefully assessed for the correct implementation of clocking, reset, RAMs, ROMs and any analogue functions.




Click here to view our show-case IP product, a low power, high throughput 2D DCT/IDCT which also features a design walk-through to fully illustrate our capabilities.