ATPG Development Service


The provision of the ATPG development service is divided into four phases as depicted below.






Phase 1 - Preparation for ATPG
The first phase is one of preparation and is best carried out when Synthesis is beginning as a netlist is required. The netlist does not have to be free of bugs and an early version is adequate. The SDF file is not required during this phase. The Test Strategy should have been generated earlier than this, but if it does not yet exist, then it should be put in place at this time.

It is important to gather all the testability requirements as the first step of this phase, both from the vendor regarding their sign-off requirements, and from the customer who needs to consider early in the project all the options available to them from today's advanced tools. The structure of the design needs analysis, and sub-blocks like RAMs, ROMs, analogue blocks and legacy non-scan IP need assessment, and a test strategy for the chip must be put in place.




Phase 2 - Testability Analysis and Debug
The second phase is one of analysis of data gathered during the first phase, with the aim of fixing testability DRC errors and raising the possible fault coverage. Suggestions may be made for RTL and/or synthesis script changes. Stuck-at, iddq, path delay and transition faults are covered as required. If fault coverage for some sections of the chip are too low, fault grading of functional vectors using Flextest may be considered by the customer.

Once the SDF file is available, SDF annotated scan chain simulation may take place. Clock tree delays may be artificially balanced initially.




Phase 3 - Automation of ATPG and Vector Set Simulation
Once adequate fault coverage has been achieved and the simulation of scan patterns debugged, the Tester vector sets may be created. These vectors sets require simulation.

The generation of the scan patterns and the saving of these scan patterns in vector sets is then automated, along with any Vendor specified pre and post processing of the netlist and vector sets.




Phase 4 - Monitoring of ATPG Coverage and Vector Set Simulation
The automated scripts developed in stage 3 should be run for every major release of the netlist, i.e. pre-layout, STA fixed versions after timing closure, ECO netlists if these are necessary, and the final post-layout netlist.

The verified vector sets are then signed-off with the Vendor.



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