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This black box specification is high level, and does not detail IO ports (please see the datasheet). It was intended as a stake in the ground for assessing different architectures.

Power

The DCT/IDCT function typically has a very high logic activity. Therefore power savings in this function could translate into large power savings in the full product. This is valuable in battery operated devices, or when a reduction in power dissipation enables a lower power-rated (and thus cheaper) package to be used for the chip.

Area

Although area is not the highest priority, it should be minimised with due regard to power and accuracy.

Clock Speed

A clock speed has not been specified. In general, a lower clock speed can mean lower power operation, depending on logic area and activity.

Data format and Accuracy

The data input to the 2D-DCT shall be 2's complement 9bit data which has already been converted from the standard offset binary YCrCb video data. Data shall be input as an 8x8 block of either Y, Cr or Cb. This will enable use in MPEG applications. 8bit data input shall also be supported for JPEG applications.

The data output from the 2D-DCT shall be 2's complement 12bit data, if possible to +/- 0.5 LSB accuracy, but at least to +/- 1 LSB accuracy.

The data input to the 2D-IDCT shall be 2's complement 12bit data.

The data output from the 2D-IDCT shall be 2's complement 9bit data, if possible within +/- 0.5 LSB of the data originally input to the 2D-DCT, but at least to +/- 1 LSB accuracy. The IDCT shall be IEEE 1180-1990 compliant.

Data Rates

While data rates are very application specific, a point of comparison has been taken as VGA resolution at 25fps. This equates to 7.68 Million pixels per second, and assuming 4:2:2 component video, 240 thousand 8x8 blocks per second. This provides a means of comparing clock speed and power with other available DCT/IDCT functions.

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